Input/output pads in conventional integrated circuit devices are typically arranged on one or more sides of a chip. Conventional pad layout structures are discussed in U.S. Pat. No. 5,072,280 entitled Resin Sealed Integrated Circuit and Korean Patent Publication No. 1999-40435 entitled Memory Device with a Plurality of Memory Banks Sharing Input/Output Lines, the disclosures of which are hereby incorporated herein by reference as if set forth in their entirety.
Conventional integrated circuit memory devices are configured to read data from a memory cell array and transfer the data to data input/output pads through peripheral circuits. As discussed above, the input/output pads are typically arranged on one or more sides of the chip, thus the length of the data lines associated with an array bank situated close to the input/output pads may be different, i.e. shorter, than the length of the data lines associated with an array bank situated farther from the data input/output pads. Accordingly, the data from the array banks situated farther from the data input/output pads may experience longer delays relative to the data from the array banks situated closer to the data input/output pads, i.e, data skew problems may arise as a result of the different lengths of the data paths. The presence of this delay skew may, for example, limit an operating frequency of an integrated circuit memory device.